A Surrogate Model for Variation-Aware Clock-Mesh Analysis and Design-Space Exploration using Graph Neural Networks
Muhammad Hadir Khan, Wajid Ali, Arya Thottiparambil Manikandan, Matthew Guthaus
Abstract
Clock meshes are widely used in high-performance VLSI systems to minimize skew and tolerate On-Chip Variation (OCV) in nanometer technologies. However, analyzing meshes is difficult because reconvergent paths and multi-source drivers prevent static timing analysis (STA) tools from handling mesh loops, making SPICE the industrial standard. SPICE simulations are accurate but slow, so clock-mesh synthesis relies on approximate models that overlook critical effects such as non-linear buffer driving caused by input slew and input skew. We propose a Graph Neural Network (GNN) based surrogate model of the clock mesh with a new graph representation and a new architecture that predicts power while also improving the delay and slew predictions at the sinks and capturing the skew histogram under OCV. Trained on SPICE data and tested on unseen real designs, our model achieves average errors of $3.40$~ps in delay, $4.14$~ps in slew and $4.46$~ps in skew, compared with $6.28$~ps, $12.35$~ps, and $11.62$~ps for our prior model, and $74.37$~ps delay and $27.51$~ps skew for the approximate method used in current state-of-the-art works. Our model predicts power within $3.4\%$ of SPICE on average, while delivering $18\times$-$1706\times$ speed-ups over the approximate method under OCV modeling, enabling faster and more accurate clock-mesh design-space exploration. A case study on a real design further shows that our surrogate model finds buffering candidates that, at a balanced tradeoff, improves $99^{\text{th}}$-percentile skew by $49.1\%$, reduces power by $25.7\%$, and reduces area by $37.3\%$ at the cost of a $6.8\%$ increase in $99^{\text{th}}$-percentile maximum slew as compared to the state-of-the-art work.